1. Field of Invention
The present invention relates generally to methods of fabricating integrated circuits. More precisely, the use of dummy lines to commonize the pattern densities of integrated circuits is disclosed to improve the removal rate consistency during chemical mechanical polishing.
2. Description of the Prior Art
In the art of fabricating semiconductors, it is important that the surface of a semiconductor wafer be planar in order to meet the requirements of optical projection lithography. Two common techniques used to achieve planarity on a semiconductor surface are a Spin-On Glass (SOG) etchback process and a Chemical Mechanical Polishing (CMP) process. Although both processes improve planarity on the surface of a semiconductor wafer, CMP has been shown to have a higher level of success in improving global planarity. The assurance of planarity is crucial to the lithography process as the depth of focus of the lithography process is often inadequate for surfaces which do not have a consistent height.
A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles. Semiconductor wafers are mounted on a polishing fixture such that the wafers are pressed against the polishing pad under high pressure. The fixture then rotates and translates the wafers relative to the polishing pad. The polishing slurry assists in the actual polishing of the wafers. Abrasive forces are created by the motion of the wafer against the polishing pad. While the pH of the polishing slurry controls the chemical reactions, e.g. the oxidation of the chemicals which comprise an insulating layer of the wafer, the size of the silicon dioxide particles controls the physical abrasion of surface of the wafer. The polishing of the wafer is accomplished when the silicon dioxide particles abrade away the oxidized chemicals.
The amount of material polished during the CMP process has been shown to be dependent upon the pattern density of the topography of the layers being polished, i.e. the amount of material polished depends on the concentration of raised areas on the layer being polished. In the art of polishing semiconductor wafers, the polishing time and the downforce exerted on a wafer by a polishing fixture are typically fixed, regardless of the topography of the particular layer being polished. It is well known in the art that the relationship between the removal rate of material during polishing, the downforce exerted on the wafer by a polisher, and the surface area which is polished is best expressed by Preston's law. Preston's law states that the removal rate of material from a wafer is proportional to the downforce exerted on the wafer and inversely proportional to the surface area of the wafer which comes into contact with the polisher. Generally, for a fixed downforce, Preston's law shows that the removal rate of material increases as the polished surface area decreases, and vice versa. As such, the material removal rate during CMP can very well be inconsistent from integrated circuit to integrated circuit, as well as from layer to layer on a single wafer containing at least one integrated circuit, since the concentration of raised areas is typically widely variant from layer to layer.
A typical semiconductor wafer has at least one integrated circuit with a plurality of trace layers which contain a multiplicity of active conductive traces. However, for illustrative purposes, the semiconductor wafers diagrammatically illustrated in FIGS. 1A and 1B include only a single integrated circuit with very few active conductive traces. FIG. 1A is a diagrammatic illustration of the surface of a semiconductor wafer 10 which includes an integrated circuit 20. The trace layer shown on integrated circuit 20 has one raised area 22. A raised area 22 is normally an active conductive trace, which electrically couples associated electrical elements of an integrated circuit 20, on a trace layer over which an insulating layer has been deposited. FIG. 1B is a diagrammatic illustration of the surface of a semiconductor wafer 30 which includes an integrated circuit 40. The layer shown on integrated circuit 40 is comprised of two raised areas 42a and 42b. The illustrations could very well represent different layers of the same wafer and integrated circuit; however, for ease of explanation, they will be considered to represent different wafers which, in this case, contain different integrated circuits. Assuming that wafer 10 and wafer 30 have the same area, and further assuming that integrated circuit 20 is equal in area to integrated circuit 40, it is clear that the topography of integrated circuit 40, which is comprised of two raised areas 42a and 42b, has a higher pattern density than the topography of integrated circuit 20, which is comprised of one raised area 22.
In the CMP process, with a fixed polishing time and a fixed downforce, a greater surface area of material will be polished on wafer 30 than on wafer 10, due to the fact that wafer 30 has a higher concentration of raised areas 42a and 42b which come into contact with a polisher. It follows, from Preston's law, that for a fixed polishing time, the depth of material removed from wafer 30 will be less than the depth of material removed from wafer 10. In other words, if the height of the raised areas 22 and 42 is initially the same, after the CMP process, the height of raised area 22 on wafer 10 will be lower than the height of the raised areas 42a and 42b on wafer 30, as the depth of material removed from raised area 22 is greater than the depth of material removed from raised areas 42a and 42b.
From a process control standpoint, there are many difficulties with the CMP process. Some of these difficulties are due to the fact that the amount of material removed from a wafer during the CMP process is dependent upon several different factors, including the total surface area which is polished and the polishing time. Maintaining consistency in the material removal rate in the CMP process, thereby maintaining a consistent height of raised areas after the CMP process, is crucial both to assure the electrical performance of the integrated circuits being fabricated and to control the process performance of the integrated circuits. The depth of material removed from every layer of every product needs to be consistent in order to maintain a consistent height of raised areas after the CMP process. Occasionally, the polishing time of the CMP process may be adjusted before each layer of a wafer is polished in order to enable the same depth of material to be removed from every layer of every product. The downforce exerted by the polisher may also occasionally be varied in order to control the material removal rate during the CMP process. From a manufacturability standpoint, however, these solutions are less than desirable as both are time-consuming and costly.
Although the conventional CMP process is effective in planarizing the surface of a semiconductor wafer, it would be desirable to find a time and cost efficient method for removing a consistent depth of material from every layer of every product, while utilizing the same CMP process.